Fabrication of a magnetic-tunnel-junction-based nonvolatile logic-in-memory LSI with content-aware write error masking scheme achieving 92% storage capacity and 79% power reduction

作者：Natsui Masanori^*; Tamakoshi Akira; Endoh Tetsuo; Ohno Hideo; Hanyu Takahiro

来源：Japanese Journal of Applied Physics, 2017, 56(4): 04CN01.

DOI：10.7567/JJAP.56.04CN01

A magnetic-tunnel-junction (MTJ)-based video coding hardware with an MTJ-write-error-rate relaxation scheme as well as a nonvolatile storage capacity reduction technique is designed and fabricated in a 90 nm MOS and 75nm perpendicular MTJ process. The proposed MTJ-oriented dynamic error masking scheme suppresses the effect of write operation errors on the operation result of LSI, which results in the increase in an acceptable MTJ write error rate up to 7.8 times with less than 6% area overhead, while achieving 79% power reduction compared with that of the static-random-access-memory-based one.

• 出版日期2017-4