A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS

作者：Tyshchenko Oleksiy^*; Sheikholeslami Ali; Tamura Hirotaka; Kibune Masaya; Yamaguchi Hisakatsu; Ogawa Junji

来源：IEEE Journal of Solid-State Circuits, 2010, 45(6): 1091-1098.

DOI：10.1109/JSSC.2010.2047156

• Clock and data recovery
• CDR
• ADC-based CDR
• feed-forward CDR
• blind-sampling CDR
• all-digital CDR

This paper presents an ADC-based CDR that blindly samples the received signal at twice the data rate and uses these samples to directly estimate the locations of zero crossings for the purpose of clock and data recovery. We successfully confirmed the operation of the proposed CDR architecture at 5 Gb/s. The receiver is implemented in 65 nm CMOS, occupies 0.51 mm(2) and consumes 178.4 mW at 5 Gb/s.

• 出版日期2010-6