A Low-Power Multiplier Using an Efficient Single-Supply Voltage Level Converter

作者：Moghaddam Majid; Moaiyeri Mohammad Hossein^*; Eshghi Mohammad; Jalali Ali

来源：Journal of Circuits, Systems, and Computers, 2015, 24(8): 1550124.

DOI：10.1142/S0218126615501248

• Low-power design
• dual-V-DD
• voltage level converter
• clustered-voltage scaling (CVS)
• multiplier
• power-delay product (PDP)

This paper presents a new high-performance and low-power single-supply voltage level converter (SSLC) and a new carry save array multiplier based on clustered-voltage scaling (CVS) technique for ultra-low-power applications. The multiplier operates with low and high supply voltage (V-DDL, V-DDH) and at its end stage, the proposed low-power SSLC is utilized to prevent static power dissipation at the next stage working with VDDH and to enhance the output driving capability. In the proposed SSLC, dynamically-controlled source-body voltage, reduced drain induced barrier lowering (DIBL) effect and diode-connected transistor with body-biasing have been utilized properly in order to reduce the power consumption significantly without considerable speed degradation. The results of the simulations conducted using Cadence with standard 90-nm CMOS technology demonstrate the superiority of the proposed multiplier utilizing the proposed LC in terms of static and total power consumptions as well as power-delay product (PDP) as compared to the multipliers utilizing the previous level converters (LCs) and the single supply multiplier. It is worth mentioning that the static power, total power and PDP of the proposed low-power multiplier are on average 75%, 73% and 16%, respectively lower than the single-supply multiplier.

• 出版日期2015-9