A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture

作者：Zhang Xiaowei; Hu Qingsheng^*

来源：Chinese Journal of Semiconductors, 2011, 32(4).

DOI：10.1088/1674-4926/32/4/045009

• 10 B/8 B decoder
• CMOS technology
• Core area
• Critical Paths
• Eye diagrams
• Fully pipelined
• high-speed
• Measurement results
• Peak-to-peak jitter
• pipelined
• Pipelined architecture
• Power supply
• Proposed architectures
• SerDes
• Standard cell
• Total power consumption

A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before, and so its speed is improved greatly. Based on the proposed architecture, a 10 B/8 B decoder is implemented based on standard cells in 0.18 μm CMOS technology with a core area of 375 × 375 μm2. Measurement results show that the decoder works well and its speed can be up to 6.25 Gbps. At a 1.8 V power supply, the total power consumption is 21.6 mW during 6.25 Gbps operation and the peak-to-peak jitter in the eye diagram is 177.8 ps.

• 出版日期2011
• 单位东南大学