A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC

作者：Manzano Miguel A^*; Michell Juan A; Ruiz Gustavo A

来源：Journal of Signal Processing Systems for Signal Image and Video Technology, 2013, 70(1): 59-73.

DOI：10.1007/s11265-012-0660-z

• H.264
• Integer transform
• Quantization
• Transform coding
• ASIC processor

This paper presents an ASIC processor chip for real-time implementation of the computing of the complete process of forward transform, quantization, inverse transform, dequantization, and reconstruction of a 16 x 16 macroblock in full compliance with the H.264/AVC video coding standard. This processor is capable of processing 4 x 4 blocks without interruption, with a parallelism in the data-path of 16 data/cycle, in a pipeline architecture with the twofold aim of achieving high operation frequency and high throughput. To implement the four 4 x 4 transforms and two 2 x 2 transforms required in the H.264/AVC coding system, two configurable multitransform direct 2-D architectures are used, one for forward and another for inverse. Moreover, a reduction in hardware is achieved by reformulating of quantization and dequantization equations and appropriately adjusting the datapath bus widths. A prototype of this processor chip was fabricated in the HCMOS9 STMicroelectronics 130 nm standard cell technology. The latency for 16 x 16 macroblocks is 26 clock cycles in normal mode and 42 in Intra 16 x 16 mode with a maximum operating frequency of 280 MHz and a throughput of 4,480 Mpixels/s. As a result, our processor chip is able to support the UHDTV 7680 x 4320@60 Hz (3 G sample/s) format requirement.

• 出版日期2013-1