A Time Domain Reflectometer with 100 ps precision implemented in a cost-effective FPGA for the test of the KLOE-2 Inner Tracker readout anodes

作者：Bencivenni G; Czerwinski E; De Lucia E; De Robertis G; Domenici D; Erriquez O; Fanizzi G^*; Felici G; Liuzzi R; Loddo F; Mongelli M; Morello G; Ranieri A; Valentino V

来源：NUCLEAR INSTRUMENTS %26 METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, 2013, 698: 185-191.

DOI：10.1016/j.nima.2012.10.023

• Time Domain Reflectometer (TDR)
• Field Programmable Gate Array (FPGA)
• Tapped delay line
• Statistical Code Method
• Micro-strip

A Time Domain Reflectometer implemented in a single cost-effective Field Programmable Gate Array device is shown to achieve a precision around 100 ps. The Time to Digital Converter section of the device is based on a tapped delay line followed by an encoder and shows both Differential and Integral Non-Linearity below one least significant bit. The same Field Programmable Gate Array houses an 8051 8-bits microprocessor, for the control of the pulse signals generation, the acquisition and the first treatment of raw data. Principles of operation, architecture, performance and preliminary trials on the prototype are presented in this paper. As an example of possible application, the proposed circuit has been usefully used to perform the quality control of the micro-strip anodic planes of the Gas Electron Multiplier Inner Tracker of the KLOE-2 experiment.

• 出版日期2013-1-11