Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model

作者：Gharehbaghi Amir Masoud^*; Fujita Masahiro

来源：IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2014, E97D(4): 852-863.

DOI：10.1587/transinf.E97.D.852

• design error diagnosis
• design error correction
• micro architecture debugging
• formal verification
• processors

This paper presents a method for automatic rectification of design bugs in processors. Given a golden sequential instruction-set architecture model of a processor and its erroneous detailed cycle-accurate model at the micro-architecture level, we perform symbolic simulation and property checking combined with concrete simulation iteratively to detect the buggy location and its corresponding fix. We have used the truth-table model of the function that is required for correction, which is a very general model. Moreover, we do not represent the truth-table explicitly in the design. We use, instead, only the required minterms, which are obtained from the output of our backend formal engine. This way, we avoid adding any new variable for representing the truth-table. Therefore, our correction model is scalable to the number of inputs of the truth-table that could grow exponentially. We have shown the effectiveness of our method on a complex out-of-order superscalar processor supporting atomic execution of instructions. Our method reduces the model size for correction by 6.0x and total correction time by 12.6x, on average, compared to our previous work.

• 出版日期2014-4