A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS

作者：Chang Pei Yao^*; Lin Tay Jyi; Wang Jinn Shyan; Yu Yen Hsiang

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2012, 59(12): 908-912.

DOI：10.1109/TCSII.2012.2231031

• Register file design
• subthreshold design
• ultra-wide dynamic voltage scaling (UDVS)

This brief presents a 4R/2W register file design for two-issue microprocessors with ultra-wide dynamic voltage scaling. A full-N separated read port has been proposed to save similar to 19% area and to improve 4.5 similar to 10.4% performance of state-of-the-art 1P3N designs for subthreshold operations. In addition, a reconfigurable write scheme has been proposed to utilize the unused write port in the energy-efficient mode with single-issue execution for similar to 18% write noise margin improvement. A test chip has been designed and fabricated using the TSMC 65-nm GP process, of which a minimum operating voltage of 148 mV has been measured.

• 出版日期2012-12