A 0.5-V low power analog front-end for heart-rate detector

作者：Suda Naveen; Nishanth P V; Basak Debajit; Sharma Durshee; Paily Roy P^*

来源：Analog Integrated Circuits and Signal Processing, 2014, 81(2): 417-430.

DOI：10.1007/s10470-014-0402-1

• Low power
• 0.5 V operation
• Second order sigma delta modulator
• Switched opamp
• Switched capacitor filter

This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 mu m CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8-32 Hz. To digitize the analog signal, a low power second-order I I" pound ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, I I" pound modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 mu W from 0.5 V supply.

• 出版日期2014-11