A Fault-Tolerant Architecture with Error Correcting Code for the Instruction-Level Temporal Redundancy

作者：Yan Chao; Dai Hongjun^*; Chen Tianzhou

来源：IEICE Transactions on Information and Systems, 2012, E95D(1): 38-45.

DOI：10.1587/transinf.E95.D.38

• soft errors
• fault tolerance
• double execution
• instruction reuse buffer
• fast error correcting code

Soft error has become an increasingly significant concern in modern micro-processor design, it is reported that the instruction-level temporal redundancy in out-of-order cores suffers an performance degradation up to 45%. In this work, we propose a fault tolerant architecture with fast error correcting codes (such as the two-dimensional code) based on double execution. Experimental results show that our scheme can gain back IPC loss between 9.1% and 10.2%, with an average around 9.2% compared with the conventional double execution architecture.

• 出版日期2012-1
• 单位浙江大学; 山东大学