A High-Linear CMOS Down Conversion Mixer Using Adjusting the Second and Third-Order Harmonic in Transconductance Stage

作者：Amiri Mina^*; Abrishamifar Adib

来源：Journal of Circuits, Systems, and Computers, 2015, 24(1): 1550002.

DOI：10.1142/S0218126615500024

• Down conversion
• mixer
• linearity
• IIP3

In this paper a new high-linear CMOS mixer is proposed. A well-known low voltage CMOS multiplier structure is used for mixer application in this paper and its linearity is provided by adjusting the value of a resistor, sizing the aspect ratio of a PMOS transistor and adding a proper value of inductor at the input stage. In simulation, a supply voltage as low as 1V is applied to the circuit. Simulation results of improved mixer in a 0.18-mu m CMOS technology illustrate 14 dB increases in IIP3 and also an increase around 1.4 dB is obtained in conversion gain. Furthermore, additional components which are used for improving linearity would not increase the power consumption and area significantly.

• 出版日期2015-1