A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

作者：Hoeppner Sebastian; Haenzsche Stefan; Ellguth Georg; Walter Dennis; Eisenreich Holger; Schueffny Rene

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2013, 60(11): 741-745.

DOI：10.1109/TCSII.2013.2278123

• All-digital phase-locked loop (ADPLL)
• bang-bang phase-frequency detector (PFD)
• clock generator
• lock time

This brief presents a bang-bang all-digital phase-locked loop (ADPLL) clock generator for multiprocessor system-on-chip applications in Globalfoundries 28-nm superlow-power CMOS technology. The circuit features a single-shot phase synchronization scheme for instantaneous phase lock after power-up. This feature is used for fast frequency search during lock-in, resulting in less than 1-mu s initial lock time and the capability of instantaneous restart. The ADPLL provides a wide range of output clocks from 83 MHz to 2 GHz and exhibits 31-ps accumulated jitter with 3-ps period jitter at 2 GHz. It occupies an area of only 0.00234 mm(2) and consumes 0.64 mW from a 1.0-V supply.

• 出版日期2013-11