AnalysisofPerformanceBenefitsofMultitierGate-LevelMonolithic3-DIntegrate dCircuits

作者：Hong Inki; Kim Dae Hyun^*

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(8): 1614-1626.

DOI：10.1109/TCAD.2017.2768427

• Monolithic 3-D integration
• performance analysis
• prediction
• reversal of critical paths (RCP)

Vertical interconnects used in monolithic 3-D integrated circuits (3-D ICs), so-called monolithic interlayer vias (MIVs), are as small as local vias. Thus, redesigning an existing 2-D IC layout in a monolithic 3-D IC generally results in shorter wire length than the 2-D IC layout. In addition, MIVs have almost negligible resistance and capacitance, so their impact on signal delay is very small. Thus, redesigning a 2-D IC layout in a monolithic 3-D IC is expected to improve its performance significantly. Some researchers designed several monolithic 3-D 1C layouts and showed their timing benefits in the literature. In this paper, we present analytical models for performance (timing) benefits of multitier gate-level monolithic 3-D ICs. The analytical models we develop in this paper can be used to quickly estimate the performance benefits multitier gate-level monolithic 3-D integration provides without physically redesigning 2-D IC layouts in 3-D.

• 出版日期2018-8