A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop

作者：Chen Xin^*; Yang Jun; Shi Long xing

来源：IEICE - Transactions on Electronics, 2008, E91C(12): 1971-1975.

DOI：10.1093/ietele/e91-c.12.1971

• digitally controlled phase-locked loop (DCPLL)
• frequency divider
• frequency search algorithm

A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore. to reduce the power consumption. the frequency divider is reused as a frequency detector during the frequency acquisition. and reused as a time-to-digital converter module during the phase acquisition. To verity the proposed algorithm and architecture a DCPLL design is implemented by SMIC 0.18 mu m 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200 MHz. The corresponding power consumption of DCPLL is 3.71 mW.

• 出版日期2008-12
• 单位东南大学