An nMOS Static ESD Power Supply Clamp With Thyristor Delay Element and 180 pA Leakage in 65 nm CMOS Technology

作者：Elghazali Mahdi^*; Sachdev Manoj; Opal Ajoy

来源：IEEE Transactions on Device and Materials Reliability, 2018, 18(1): 97-104.

DOI：10.1109/TDMR.2018.2802378

• Electrostatic discharge (ESD)
• ESD power supply clamps
• human body model (HBM)
• charged device model (CDM)
• leakage
• transmission-line pulse (TLP) testing

Electrostatic discharge (ESD) is a well-known problem in integrated circuits (ICs) that impacts the reliability, yield, and cost of the ICs. In this paper, a low-leakage, static ESD clamp is proposed in 65-nm CMOS technology. CMOS thyristor was added as a delay element to the conventional diode triggered static clamp to improve its on time during the ESD stress, while the thick oxide transistors were used to reduce the leakage under normal operating conditions. The proposed clamp was characterized at different process corners under ESD stresses. The transmission-line pulse measurement results show that the clamp is capable of handling 3.21 A of current, and has 180 pA as the leakage current at room temperature. Measurement results exhibit that the clamp is robust against false triggering and the latch-up. The proposed clamp passes both +3.5 and -4.5 kV HBM stresses and passes +700 and -450 V CDM stresses.

• 出版日期2018-3