摘要
We present analysis, optimization, design and characterization of an integrated passive analog phase shifter at 24 GHz in a commercially available 45 nm RF-CMOS process. The design is based on a well-known RC bridge topology, which was optimized for maximum phase shift and minimal amplitude response variation versus phase and frequency. Phase is controlled by varying DC voltage on a varactor, resulting in 60 degrees maximum phase shift with 0.1 dB amplitude variation at 24 GHz. The size of the phase shifter circuit excluding pads and input/output buffers is 40 x 50 mu m(2).
- 出版日期2011-10