Area Optimization of Timing Resilient Designs Using Resynthesis

作者：Huang Hsin Ho^*; Cheng Huimei; Chu Chris; Beerel Peter A

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(6): 1197-1210.

DOI：10.1109/TCAD.2017.2748001

• Circuit and systems
• circuit synthesis
• integrated circuit synthesis

Timing resilient designs can remove variation margins by adding error detecting logic (EDL) that detects timing errors when execution completes within a resiliency window. Speeding up near-critical-paths during logic synthesis can reduce the amount of EDL needed but at the cost of increasing logic area. This creates a logic optimization strategy called resynthesis. This paper proposes four alternatives to optimize resilient designs through resynthesis. The first is a brute force approach that explores speeding up all combinations of near-critical paths and produces good results but is computationally impractical for complex circuits. The second is a naive brute-force (BF) approach in which near-critical paths are sped up one end-point at a time. It is much faster than the BF approach because it does not explore the benefits of speeding up multiple end-points simultaneously and thus provides a quick-and-dirty lower bound for the benefits of resynthesis. The third is a geometric program-based iterative algorithm (GPIA) that achieves area reductions that compare favorably across all four approaches. The GPIA algorithm completes within 24 h for all examples and the average area reduction is up to 16%. Because the run-time required to solve this mathematical model can still be long; however, we propose a fourth approach that involves creating a virtual resynthesis cell library that tries to trick the synthesis tool to understand EDL overhead and optimize total area quickly and automatically. This approach obtains an average of approximately two-third of the area reductions of the GPIA approach with fast run times associated with only a single synthesis run.

• 出版日期2018-6