A Proposal for Yield Improvement with Power Tradeoffs in CMOS LNAs

作者：Gonzalez J L^*; Cruz J C^*; Moreno R L^*; Vazquez D^*

来源：IEEE Latin America Transactions, 2016, 14(1): 13-19.

DOI：10.1109/tla.2016.7430056

• CMOS
• low-noise amplifier (LNA)
• variability
• yield
• radio-frequency receiver
• programmable structure

This paper investigates the capability of an architecture with digitally controllable gain and power consumption, for mitigating the effects of process variations on CMOS Low-Noise Amplifiers (LNAs). A 130-nm 1.2-V LNA with the proposed architecture is designed, based on the analysis of variability in LNAs with a traditional architecture under different biasing currents conditions, and the corresponding effects in the performance of a complete receiver context. Two different adjusting strategies are evaluated, which could be implemented with already reported Built-in Self-Test (BIST) circuits. Results show that the proposed architecture allows yield enhancement with low-power operation compared to traditional LNAs.

• 出版日期2016-1