A Functional Unit and Register Binding Algorithm for Interconnect Reduction

作者：Kim Taemin^*; Liu Xun

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(4): 641-646.

DOI：10.1109/TCAD.2010.2042903

• DSP synthesis
• high level synthesis
• interconnect
• resource binding
• synthesis

This paper describes a simultaneous register and functional unit (FU) binding algorithm in high level synthesis. Our algorithm targets the reduction of multiplexer inputs, shortening the total length of global interconnects. Specifically, our algorithm maximizes the interconnect sharing among FUs and registers by considering flow dependences, common primary inputs, and common register inputs among operations. Experimental results have shown that our scheme achieves more than 20% multiplexer input count reduction, on average, over previously proposed algorithms. Our approach delivers a 18% wirelength reduction of global interconnects with minor area overhead.

• 出版日期2010-4