Dual CDS scheme embedded in SAR-based ADCs for low-noise CMOS imagers without a PGA

作者：Kim M K; Hong S K; Gou J; Kwon O K^*

来源：Electronics Letters, 2017, 53(1): 16-17.

DOI：10.1049/el.2016.3706

• analogue-digital conversion
• readout electronics
• CMOS digital integrated circuits
• dual CDS scheme
• SAR-based ADCs
• low-noise CMOS imagers
• dual correlated double sampling scheme
• successive approximation register
• single-slope analogue-to-digital converters
• readout channel
• noise reduction
• capacitor digital-to-analogue converter
• DAC
• CIS process technology
• signal-to-noise-distortion ratio
• size 90 nm

A dual correlated double sampling (CDS) scheme, which can be embedded into a successive approximation register (SAR) or SAR/single-slope analogue-to-digital converters (ADCs) for low-noise CMOS imagers without the use of a power-consuming programmable gain amplifier (PGA) is proposed. To reduce the noise of the readout channel, the proposed dual CDS scheme removes the sampling error, which occurs in the capacitor digital-to-analogue converter (DAC), by storing only a reset voltage of the pixel into the capacitor DAC. In addition, without using the PGA, it amplifies the output of the readout channel by controlling the reference voltages of the ADC. The readout channel using the proposed CDS scheme was designed using a 90 nm CMOS imager process technology. The simulation results show that the signal-to-noise-distortion ratio of the readout channel using the proposed dual CDS scheme is 81.8 dB, which is an improvement of 10.8 dB over the digital CDS scheme. In addition, the output of the readout channel is amplified without the use of a PGA.

• 出版日期2017-1-5