A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS

作者：Grover Anuj^*; Visweswaran G S; Parthasarathy Chittoor R; Daud Mohammad; Turgis David; Giraud Bastien; Noel Jean Philippe; Miro Panades Ivan; Moritz Guillaume; Beigne Edith; Flatresse Philippe; Kumar Promod; Azmi Shamsi

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64(9): 2438-2447.

DOI：10.1109/TCSI.2017.2705116

• Low voltage SRAM
• wide voltage range SRAM
• voltage scaling
• FDSOI
• write assist
• multiple wordline
• bit-interleaved SRAM

An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35-1.2 V at all process corners. A differential read asymmetric 8 T memory cell and a data dependent differential supply and body modulation write assist scheme are proposed. We also propose a layout that reduces metal capacitance of wordlines by 54% and also enables bit-interleaving. The proposed assist scheme can be combined with conventional assist schemes to further lower minimum write operational voltage of the SRAM by 70-130 mV at iso-performance without causing reliability concerns. A 32 kb instance is fabricated in 28-nm UTBB-FDSOI technology and efficiency of the proposed scheme is demonstrated with lowest write voltage of 0.32 V. Multiple read assist schemes have been used to simultaneously lower read voltage to 0.35 V. 50 MHz operation is measured when integrated in a DSP processor at 0.358 V. Low voltage and wide voltage range figure of merits are also defined to benchmark the proposed solutions with other works.

• 出版日期2017-9
• 单位中国地震局