A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-V-dd SoCs

作者：Vartziotis Fotis^*; Kavousianos Xrysovalantis; Georgiou Panagiotis; Chakrabarty Krishnendu

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36(11): 1911-1924.

DOI：10.1109/TCAD.2017.2664062

• Dynamic voltage-frequency scaling (DVFS)
• system-on-chip (SoC) testing
• test scheduling
• test-access-mechanism (TAM)
• voltage islands

The use of multiple voltage levels introduces new challenges for testing multi-V-dd systems-on-chip (SoCs). Time-division-multiplexing (TDM) tackles many of these challenges and offers very effective test-schedules. However, the effectiveness of TDM for minimizing test time depends on the test-access-mechanism (TAM) in the SoC. Single-V-dd TAM optimization techniques consider neither the highly constrained test environment of multi-V-dd SoCs nor the benefits provided by TDM, therefore they are not suitable for multi-V-dd SoCs. In this paper, we propose the first TAM optimization technique for multi-V-dd SoCs. The proposed method exploits unique scheduling opportunities and flexibility offered by TDM, and by the means of a branch-&-bound approach, it quickly identifies the most effective TAM configurations. Experiments using large benchmark SoCs as well as SoCs from industry highlight the benefits of the proposed technique on multi-V-dd designs, for both single-site and multisite test applications.