A semi-synchronous SAR ADC

作者：Tong Tao^*; Hanumolu Pavan K; Temes Gabor C

来源：Analog Integrated Circuits and Signal Processing, 2012, 71(3): 407-410.

DOI：10.1007/s10470-011-9769-4

• Analog-to-digital converters
• Successive-approximation conversion
• Dynamic clocking scheme

A semi-synchronous clocking scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). The conversion time is dynamically allocated to the comparator decision and to the DAC settling in every bit cycle. This significantly improves the conversion speed.

• 出版日期2012-6