Analysis and optimization of safe-operating-area of LUDMOS transistors based on 0.18 mu m SOI CMOS technology

作者：Cortes I^*; Toulon G; Morancho F; Urresti J; Perpina X; Villard B

来源：Semiconductor Science and Technology, 2010, 25(4): 045013.

DOI：10.1088/0268-1242/25/4/045013

This paper is focused on the design and optimization of power LDMOS transistors (V(BR) > 120 V) with the purpose of integrating them with a new generation of smart-power technology based upon 0.18 mu m SOI-CMOS technology. Different LDMOS design structures with optimal R(on-sp)/V(BR) trade-off have been analyzed in order to compare their electrical safe-operating-area (SOA). The influence of some important design parameters such as the STI length (L(STI)) and technological concerns such as the P-well and N-well mask position distance is also exhaustively analyzed in this work.

• 出版日期2010-4