Design and Analysis of a Low Loss, Wideband Digital Step Attenuator With Minimized Amplitude and Phase Variations

作者：Song Ickhyun^*; Cho Moon Kyu; Cressler John D

来源：IEEE Journal of Solid-State Circuits, 2018, 53(8): 2202-2213.

DOI：10.1109/JSSC.2018.2827934

• Attenuation/phase error compensation
• attenuator
• digital step attenuator (DSA)
• insertion loss (IL)
• modified switched T-type
• passive
• reduced switched T-type
• silicon-germanium (SiGe) BiCMOS
• wideband

A compact, low loss, wideband digital step attenuator (DSA) is presented. The proposed DSA utilizes amplitude/phase-compensated T-type attenuator cells, in which the locations of poles and zeros are manipulated for minimizing variations in attenuation and phase. In addition, the reduced T-type attenuator cells that eliminate series switch transistors are used to achieve low insertion loss (IL). These techniques provide wideband (dc-20 GHz) operation for the DSA, with significantly decreased attenuation/phase errors and reduced IL. The DSA was implemented in a 130-nm silicon-germanium (SiGe) BiCMOS platform. The full attenuator circuit has binary-coded 6-bit digital control inputs with a least significant bit of 0.5-dB attenuation. It has a root-mean-square (rms) attenuation error of 0.37 dB and an rms phase error of 4 degrees, both at 20 GHz. The IL and the input 1-dB compression point at 10 GHz are 4 dB and 10 dBm, respectively. The active core layout area is 0.14 mm(2) (1.0 mm x 0.14 mm).

• 出版日期2018-8