A Ternary Full Adder Cell Based on Carbon Nanotube FET for High-Speed Arithmetic Units

作者：Ghanatghestani Mokhtar Mohammadi; Ghavami Behnam^*; Pedram Hossein

来源：Journal of Nanoelectronics and Optoelectronics, 2018, 13(3): 368-377.

DOI：10.1166/jno.2018.2244

• CNFET
• Ternary Logic
• Arithmetic Circuit
• High Speed
• Parallel Design
• Ternary Full Adder

Multiple values logic may potentially lead to increase efficiency of arithmetic circuits and digital signal processor. Ternary Logic can be proposed as a solution to solve power consumption concern and interconnection complexity in binary digital systems. The possibility of having several threshold voltage (V t) levels by Carbon Nanotube Field Effect Transistors (CNFETs) leading to wide use of this technology in designing of multiple value circuits. In this paper, a ternary full adder cell based on CNFET technology is proposed. The main goal of the proposed circuit is shortening data path in ternary adder circuits using a parallel design, which positively effects speed and power consumption. This circuit is designed based on the unique properties of CNFET like adjustment feature of target threshold voltage with changing the diameters of nanotubes. The proposed ternary full adder cell is compared to three other ternary full adder cells regarding to power consumption, speed and power delay product (PDP) parameters. 4-bit Ternary Ripple Carry Adders (TRCAs) are simulated to evaluate the efficiency of different ternary full adder cells used in large circuits. The results of simulation using HSPICE in 32 nm CNFET technology confirm the higher efficiency of the proposed ternary full adder cell with respect to other designs.

• 出版日期2018-3