Analysis of ADPLL jitter due to power supply noise with deterministic frequency

作者：Bai Na; Zhu Jiafeng; Chen Ming; Xia Yingcheng; Wu Xiulong^*

来源：Journal of Computational Information Systems, 2013, 9(2): 739-748.

• ADPLL
• DCO
• Noise frequencies
• Noise suppression
• Oscillation frequency
• Power-supply noise
• Simulations and measurements
• Standard CMOS process

An analytical method is presented for estimating the cycle jitter of ADPLL due to power supply noise with deterministic frequency. It leads to the conclusion that jitter heavily depends on the noise frequency and the smallest cycle jitter appears at only integer multiples of oscillation frequency. It also reveals that the relationship between the bandwidth of ADPLL and the DCOs noise-suppression varies depending on the noise frequency. Larger bandwidth does not always benefit DCOs noise suppression. Our method is utilized to study an ADPLL designed in SMIC 0.13m standard CMOS process. A comparison between the results obtained by our method and those obtained by simulation and measurement proves the accuracy of the predicted model. The measured jitters reveal that even smaller bandwidth benefits the jitter suppression when the noise frequency gets higher.

• 出版日期2013
• 单位安徽大学; 东南大学