Application of high-k dielectric stacks charge trapping for CMOS technology

作者：Sharma Satinder K^*; Prasad B; Kumar Dinesh

来源：Materials Science and Engineering B-Solid State Materials for Advanced Technology, 2010, 166(2): 170-173.

DOI：10.1016/j.mseb.2009.11.002

• Dielectric stack
• Charge trapping/detrapping

The effect of constant negative voltage stress on charge trapping and interface states of Al/HfO(2)/SiO(x)N(y)/Si structures are investigated. The reduction in the capacitance of C-t characteristics and a significant shift in C-V curves towards negative voltage axis reveal that the charge trapping/detrapping occurs at the Si/SiO(x)N(y)/HfO(2) interface and HfO(2) bulk. However, there is a relative increase in gate leakage current as a function of the voltage stress and time, owing to the trip-assisted tunnelling. It is suggested that these traps are probably Hf-OH neutral centers, originating from the breaking of bridging Si-OH and Si-NH bonds by mobile H(+) protons. This has potential application in non-volatile CMOS memory devices.

• 出版日期2010-1-25