A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM

作者：Chen Wei Cheng^*; Chen Chao Chyun; Yao Chia Yu; Yang Rong Jyi

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(1): 17-25.

DOI：10.1109/TVLSI.2015.2405548

• All-digital buck converter
• all-digital delay-locked loop (ADDLL)
• cycle-controlled delay unit (CCDU)
• digital pulsewidth modulator (DPWM)
• multithreshold-voltage band (MTVB)

This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDLL leads to the DPWM possessing a small area while maintaining high cycle resolution. Moreover, the proposed ADDLL-based cycle-controlled DPWM can achieve synchronization between its input and output. This decreases the loop delay of the proposed converter so that the system is easy to be stabilized. The prototype chips of both the ADDLL-based cycle-controlled DPWM and the all-digital buck converter are fabricated in 0.35-mu m CMOS process. Measurement results of the cycle-controlled DPWM show that the duty cycle of its output is adjustable from 1% to 99% in a 0.78% increment per step when operating at 1 MHz. The measured transition time of the all-digital buck converter is <3.5 mu s when the load current changes from 50 to 500 mA, and vice versa.

• 出版日期2016-1