Design of a deterministic link initialization mechanism for serial LVDS interconnects

作者：Schatral S^*; Lemke F; Bruening U

来源：Journal of Instrumentation, 2014, 9(03): C03022.

DOI：10.1088/1748-0221/9/03/C03022

• Data acquisition circuits
• Electronic detector readout concepts (solid-state)
• Detector control systems (detector and experiment monitoring and slow-control systems, architecture, hardware, algorithms
• databases)
• Digital electronic circuits

The Compressed Baryonic Matter experiment at FAIR in Darmstadt has special requirements for the Data Acquisition Network. One of them is deterministic latency for all the links from the back-end to the front-end, which enables synchronization in the whole read-out tree. Since the front-end electronics (FEE) contain mixed-signal circuits for processing the raw detector data, special ASICs were developed. DDR LVDS links are used to interconnect the FEEs and readout controllers. An adapted link initialization mechanism ensures determinism for them by balancing cable lengths, adjusting for phase differences, and handling environmental behavior. After re-initialization, timing must be accurate to the bit-clock level.

• 出版日期2014-3