A configurable analog buffer dedicated to a wafer-scale prototyping platform

作者：Laflamme Mayer Nicolas^*; Blaquiere Yves; Sawan Mohamad

来源：Analog Integrated Circuits and Signal Processing, 2015, 82(1): 57-66.

DOI：10.1007/s10470-014-0442-6

• Analog buffer
• Wafer-scale
• Configurable
• WaferIC
• Slew-rates

This paper concerns a novel configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems. The proposed architecture uses complementary nMOS and pMOS stage buffers, which are built with modified conventional differential pairs used for maximizing the output voltage swing. This compact analog buffer offers several slew-rate features that range from 66 up to 495 V/A mu s with a quasi-unity gain and only uses 21 transistors for a total silicon area of 0.001824 mm(2). The bandwidth of this proposed buffer can be programmed from 74 up to 194 MHz with response time up to 5.3 ns. This overall configurability allows better power management, reduces the power-supply noise injection within the wafer-scale platform, and diminishes the quiescent current.

• 出版日期2015-1