A 0.8-V 48 mu W 82dB SNDR 10-kHz Bandwidth Sigma Delta Modulator

作者：Lang Wei^*; Wan Peiyuan; Lin Pingfen

来源：5th IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2012-11-21 to 2012-11-23.

• Analog-digital conversion
• asynchronous circuits
• Sigma delta modulator
• successive approximation register
• switched capacitor circuits

This paper presents a low-power chopper stabilized discrete-time 2nd-order feed-forward Sigma Delta modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer. The weighted sum of integrated and feed-forward signals is merged with the sampling phase of the SAR quantizer to minimize the distortion sources and associated hardware overhead. The 1st integrator uses a partially switched operational amplifier biased in weak inversion to reduce power consumption. The 4-bit SAR quantizer further employs an asynchronous control scheme to reduce the loop delay and power consumption. A 0.13-mu m CMOS experimental prototype achieves 84dB dynamic range, 84dB peak SNR, and 82dB peak SNDR over an input bandwidth of 10-kHz. The total power consumption of the modulator is 48 mu W from a 0.8-V supply at an 800-kHz sampling rate.

• 出版日期2012
• 单位北京工业大学