An ultra-high speed monolithic clock recovery circuit in 0.2-A mu m GaAs process

作者：Tang Lu^*; Wang Zhigong; Qiu Yinghua; Zhang Changchun; Xu Jian

来源：Analog Integrated Circuits and Signal Processing, 2015, 83(1): 45-53.

DOI：10.1007/s10470-015-0506-2

• PLL
• Clock recovery
• CPW
• VCO
• GaAs process

This paper presents a 37 Gb/s phase locked-loop (PLL)-type clock recovery (CR) circuit designed and fabricated in 0.2-A mu m GaAs PHEMT process. The resonator of the modified LC-VCO is based on a compact circuit topology with high Q-value and better isolation. The active amplifier of the VCO is optimized with a combination of several circuit techniques to reduce phase noise and increase the operation speed. Resonant filters containing high-quality CPWs are employed in the signal preprocessor to accommodate the 37 Gb/s data rate. The measured figure of merit of the modified VCO is about -196 dBc/Hz at 37-GHz when the PLL is locked. The experimental results also demonstrate that the recovered clock signal of the CR circuit has a phase noise of -81.66 dBc/Hz at 50 kHz off the center frequency.

• 出版日期2015-4
• 单位东南大学