科研之友
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摘要
As integrated circuit technologies progress to nanoscale, process variations become relatively large and significantly impact circuit performance. The proactive management of process variation during the design process is critical to ensure effective device yield and to keep manufacturing costs down. In the present scenario, designers are searching for analogue-to-digital converter (ADC) architectures which are nanoscale CMOS processes tolerant. Expectations of the performance of ADCs are continuously increasing along with the progress of digital systems. A process and supply variation tolerant, System-on-Chip (SoC) ready, 1 GS/s, 6-bit flash ADC suitable for integration into nanoscale digital CMOS technologies is presented. The physical design of the ADC has been done using a generic 90 nm Salicide 1.2 V/2.5 V 1 Poly 9 Metal process design kit. Baseline post layout simulation results at nominal supply and threshold voltages are presented. The parasitic-extracted physical design of the ADC is then subjected to a corner-based methodology of process variation. The results show that process variation causes a maximum variation of 10.5% in the integral nonlinearity (INL) and 5.7% in the differential non-linearity (DNL), with both INL and DNL being less than 0.5 LSB. The 90 nm ADC consumes a peak power of 5.794 mW and an average power of 3.875 mW. The comparators for the ADC have been designed using the threshold inverting technique. To show technology scalability of the design, the ADC has also been presented using a 45 nm Predictive Technology Models (PTM). At 45 nm, INL = 0.46 LSB, DNL = 0.7 LSB and a sampling rate of 100 MS/s were obtained. The 45 nm ADC consumes a peak power of 45.42 mu W, and average power of 8.8 mu W.
- 出版日期2010
