A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

作者：Bulzacchelli John F^*; Menolfi Christian; Beukema Troy J; Storaska Daniel W; Hertle Juergen; Hanson David R; Hsieh Ping Hsuan; Rylov Sergey V; Furrer Daniel; Gardellini Daniele; Prati Andrea; Morf Thomas; Sharma Vivek; Kelkar Ram; Ainspan Herschel A; Kelly William R; Chieco Leonard R; Ritter Glenn A; Sorice John A; Garlett Jon D; Callan Robert; Braendli Matthias; Buchmann Peter; Kossel Marcel; Toifl Thomas; Friedman Daniel J

来源：IEEE Journal of Solid-State Circuits, 2012, 47(12): 3232-3248.

DOI：10.1109/JSSC.2012.2216414

• Active feedback
• backplane
• capacitive level shifter
• chip-to-chip communications
• current-integrating summer
• decision-feedback equalizer (DFE)
• feed-forward equalizer (FFE)
• peaking amplifier
• serial link
• source-series terminated (SST) driver
• transceiver

This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking amplifier is enhanced by adopting a structure with capacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the transceiver over a channel with 35 dB loss at half-baud frequency. In a four-port core configuration, the power consumption at 28 Gb/s is 693 mW/lane.

• 出版日期2012-12