Four-Bits-Per-Cell Operation in an HfO2-Based Resistive Switching Device

作者：Kim Gun Hwan; Ju Hyunsu; Yang Min Kyu; Lee Dong Kyu; Choi Ji Woon; Jang Jae Hyuck; Lee Sang Gil; Cha Ik Su; Park Bo Keun; Han Jeong Hwan; Chung Taek Mo; Kim Kyung Min; Hwang Cheol Seong^*; Lee Young Kuk^*

来源：Small, 2017, 13(40): UNSP 1701781.

DOI：10.1002/smll.201701781

The quadruple-level cell technology is demonstrated in an Au/Al2O3/HfO2/TiN resistance switching memory device using the industry-standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self-compliance and gradual set-switching behaviors, the device shows 6s reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 mu A. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash. A relatively minor improvement in the material and circuitry may enable even a five-bits-per-cell technology, which can hardly be imagined in NAND flash, whose state-of-the-art multiple-cell technology is only at three-level (eight states) to this day.

• 出版日期2017-10-25