A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization

作者：Llamocca Daniel^*; Pattichis Marios

来源：IEEE Transactions on Circuits and Systems for Video Technology, 2013, 23(3): 488-502.

DOI：10.1109/TCSVT.2012.2210664

• Dynamic partial reconfiguration (DPR)
• field-programmable gate-array (FPGA)
• look-up table (LUT)-based architectures

We introduce a dynamically reconfigurable framework for implementing single-pixel operations. The system relies on a multiobjective optimization scheme that generates Pareto-optimal realizations in the power/energy-performance-accuracy (PPA/EPA) spaces. The Pareto-optimal realizations and their PPA/EPA values are stored in DDR-SDRAM and can be chosen dynamically to meet time-varying constraints. Results are shown in terms of power, accuracy (peak signal-to-noise ratio) of the resulting image, and performance in frames per second. Dynamic PPA/EPA management is implemented using dynamic partial reconfiguration and dynamic frequency control.

• 出版日期2013-3