A 133 MHz Radiation-Hardened Delay-Locked Loop

作者：Sengupta Rajat^*; Vermeire Bert; Clark Lawrence T; Bakkaloglu Bertan

来源：IEEE Transactions on Nuclear Science, 2010, 57(6): 3626-3633.

DOI：10.1109/TNS.2010.2086485

• Charge pump
• delay-locked loop (DLL)
• jitter phase-locked loop (PLL)
• single-event transients (SETs)

A radiation hardened by a design delay-locked loop (DLL) architecture for quadrature phase clock generation in a 133 MHz DDR memory designed on a foundry 0.13 mu m fabrication process is presented. The DLL employs an all-digital architecture, including a hardened digital integrator using error-correction logic. The area and power overhead due to the hardening are 32% and 37%, respectively. Simulation results demonstrate that the all-digital DLL is hardened against single-event transients with no timing impact due to hardening. Layout techniques to make the DLL hardened to multiple bit upsets are also presented.

• 出版日期2010-12