A 0.8 V 48 mu W 82 dB SNDR 10-kHz BANDWIDTH Sigma Delta MODULATOR IN 0.13-mu M CMOS

作者：Lang Wei^*; Wan Peiyuan; Lin Pingfen

来源：Journal of Circuits, Systems, and Computers, 2013, 22(4): 1350027.

DOI：10.1142/S0218126613500278

• Sigma Delta modulator
• SAR
• asynchronous
• low power
• low voltage
• chopper stabilization
• switched-capacitor circuits

This paper presents a low-power low-voltage chopper stabilized discrete-time second-order feed-forward Sigma Delta modulator with an asynchronous 4-bit successive-approximation-register (SAR) quantizer. The feed-forward topology will reduce the internal signal swing, relaxing the linearity and slew rate requirements for an operational amplifier (op-amp). The analog weighted summation of feed-forward paths is merged with the sampling capacitor array of a SAR quantizer to minimize the distortion and associated hardware overhead. To achieve low power consumption, a partially switched op-amp bias in weak inversion is used for the first integrator. The energy efficiency is further improved by the asynchronous SAR 4-bit quantizer. Moreover, the asynchronous scheme will reduce loop delay caused by the summation block, the quantizer and the data weighted averaging (DWA) circuit, improving circuit stability and lowering power consumption. A 0.13-mu m CMOS experimental prototype achieves 84 dB dynamic range, 84 dB peak SNR and 82 dB peak SNDR over an input signal bandwidth of 10-kHz. The total power consumption of the modulator is 48 mu W from a 0.8V supply at an 800-kHz sampling rate.

• 出版日期2013-4
• 单位北京工业大学