Asymmetric Cache Coherency: Policy Modifications to Improve Multicore Performance

作者：Shield John^*; Diguet Jean Philippe; Gogniat Guy

来源：ACM Transactions on Reconfigurable Technology and Systems, 2012, 5(3): 12.

DOI：10.1145/2362374.2362376

• Performance
• Nonuniform workload
• cache
• memory coherency
• multicore processing
• memory management

Asymmetric coherency is a new optimization method for coherency policies to support nonuniform workloads in multicore processors. Asymmetric coherency assists in load balancing a workload and this is applicable to SoC multicores where the applications are not evenly spread among the processors and customization of the coherency is possible. Asymmetric coherency is a policy change, and consequently our designs require little or no additional hardware over an existing system. We explore two different types of asymmetric coherency policies. Our bus-based asymmetric coherency policy, generated a 60% coherency cost reduction (reduction of latencies due to coherency messages) for nonshared data. Our directory-based asymmetric coherency policy, showed up to a 5.8% execution time improvement and up to a 22% improvement in average memory latency for the parallel benchmarks Sha, using a statically allocated asymmetry. Dynamically allocated asymmetry was found to generate further improvements in access latency, increasing the effectiveness of asymmetric coherency by up to 73.8% when compared to the static asymmetric solution.

• 出版日期2012-10