A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

作者：Ishii Yuichiro; Tanaka Miki; Yabuuchi Makoto; Sawada Yohei; Tanaka Shinji; Nii Koji^*; Lu Tien Yu; Huang Chun Hsien; Chen Shou Sian; Kuo Yu Tse; Lung Ching Cheng^*; Cheng O**ert

来源：Japanese Journal of Applied Physics, 2018, 57(4): 04FB10.

DOI：10.7567/JJAP.57.04FB10

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I-read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V-min) of the proposed 256 kbit 10T DP SRAM is 0.53V in the TT process, 25 degrees C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

• 出版日期2018-4