A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC

作者：Kim Min Gyu^*; Alm Gil Cho; Hanumolu Pavan Kumar; Lee Sang Hyeon; Kim Sang Ho; You Seung Bin; Kim Jae Whui; Temes Gabor C; Moon Un Ku

来源：IEEE Journal of Solid-State Circuits, 2008, 43(5): 1195-1206.

DOI：10.1109/JSSC.2008.920329

• audio ADC
• delta-sigma ADC
• double sampling
• low voltage
• switched-RC

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 mu m CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.

• 出版日期2008-5