An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes

作者：Cui, Hangxuan; Lin, Jun^*; Wang, Zhongfeng^*

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2019, 66(3): 397-401.

DOI：10.1109/TCSII.2018.2849504

• LDPC codes
• error-floor
• post-processor
• low complexity
• performance improvement
• VLSI implementation

Error floor is one major reason for limited use of low-density parity-check (LDPC) codes in applications requiring very low bit error rate. In this brief, an efficient erasure searching post-processor (ESPP) is proposed to lower the error floor of LDPC codes. Here, when a decoding failure is detected, the most unreliable symbols in the decoder output vector are erased, then their values are re-calculated by solving a system of linear equations with a sparse coefficient matrix. Compared to the state-of-the-art post processors, the ESPP has much lower computation complexity. Simulation results show that the proposed method significantly improves the decoding performance of LDPC codes in the error-floor region. Additionally, a well-optimized hardware architecture is developed for the proposed post-processor. Algorithmic transformation and architecture optimization are well explored to reduce the hardware complexity and latency. Synthesis results demonstrate the effectiveness of the proposed architecture.

• 出版日期2019-3
• 单位南京大学