A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm(2) and 500 mW in 40 nm Digital CMOS

作者：Chen Chun Ying^*; Wu Jiangfeng; Hung Juo Jung; Li Tianwei; Liu Wenbo; Shih Wei Ta

来源：IEEE Journal of Solid-State Circuits, 2012, 47(4): 1013-1021.

DOI：10.1109/JSSC.2012.2185192

• Adaptive power and ground
• CMOS technology
• extrapolation
• high resolution
• high speed
• multiplying-digital-to-analog converter (MDAC)
• pipelined analog-to-digital converter (ADC)

A 12-bit 3 GS/s 40 nm two-way time-interleaved pipeline analog-to-digital converter (ADC) is presented. The proposed adaptive power/ground architecture eliminates the headroom limitations due to the deeply scaled power supply in nanometer CMOS technologies, while preserving the intrinsic speed of thin-oxide MOSFETs with minimum channel length for key analog blocks. Moreover, in terms of the signal swing, the proposed reference extrapolation scheme offers a smooth transition between the multiplying digital-to-analog converter stages and the last flash stage. With these two techniques, the ADC achieves a SNR of 61 dB and a DNL of -0.5/+0.5 LSB, while consuming 500 mW at a 3 GS/s sampling rate and occupying an area of 0.4 mm(2) in 40 nm CMOS process.

• 出版日期2012-4