A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS

作者：He Xun^*; Jin Xin; Wang Minghui; Zhou Dajiang; Goto Satoshi

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2011, E94A(12): 2609-2618.

DOI：10.1587/transfun.E94.A.2609

• SIMD
• cache coherence
• NoC
• GMACs
• multicore processor

This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. The SIMD cores support 8/16 bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192 GB/s low latency inter-core BW in average. The 4-ports L2 cache architecture is also designed to provide 192 GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256 KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25 mm(2) in 65 nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2 V.

• 出版日期2011-12