A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor

作者：Hwang Sewook^*; Kim Kyeong Min; Kim Jungmoon; Kim Seon Wook; Kim Chulwoo

来源：IEEE Transactions on Very Large Scale Integration Systems, 2013, 21(3): 575-579.

DOI：10.1109/TVLSI.2012.2188656

• Calibration
• dynamic frequency scaling (DFS)
• delay-locked loop (DLL)
• extendable instruction set computing (EISC)

This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of 0.5 to 8 of the reference clock, according to the workload of the EISC processor. The proposed analog self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. The self-calibrated output waveform exhibits 9.7 ps of RMS jitter and 73.7 ps of peak-to-peak jitter at 120 MHz. The prototype clock generator implemented in a 0.18-m CMOS process occupies an active area of 0.27 mm and consumes 15.56 mA.

• 出版日期2013-3