摘要

Dynamic voltage scaling is one of the most popular methods used to reduce energy consumption in today's digital electronic systems. However, addressing process, voltage and temperature variations at subthreshold voltages has become an inevitable procedure. Using a variation-sensitive and ultra low-power design, this paper proposed a novel technique capable of sensing and responding to process, voltage and temperature variations as well as dynamic voltage scaling by providing an appropriate forward body bias so that energy-delay product of the whole system was improved. Theoretical analysis for process variation probability, confirmed by post-layout HSPICE (Synopsys, Inc., Mountain View, CA) simulations for an 8-bit pipelined Kogge-Stone adder, showed that the circuit performance was enhanced in severe variations and extreme voltage scaling situation. For this adder, for example, assuming a voltage scaling from 0.8 to 0.3V and temperature changes of -15 to 75 degrees C, the proposed technique brought about a seven times less delay variation, whereas energy-delay product improved by 23% compared with a zero body biased adder.

  • 出版日期2015-2