A novel test compression algorithm for analog circuits to decrease production costs

作者：Ahmadyan Seyed Nematollah^*; Natarajan Suriyaprakash; Vasudevan Shobha

来源：Integration, the VLSI Journal, 2017, 58: 538-548.

DOI：10.1016/j.vlsi.2016.10.010

• Analog testing
• Random tree search
• Functional optimization
• Stress testing

Minimizing the manufacturing test time for ICs is one of the main keys to reducing the product cost. We introduce a methodology for automated test compression for electrical stress testing of analog and mixed signal circuits. This methodology optimally extracts only portions of a functional test that electrically stress the nets and devices of an analog circuit. We model test compression as a problem of optimizing functional of the transient response. We present a random tree based approach to fmd the minimum for these computationally hard integrals, which corresponds to the optimally compressed analog test. We demonstrate with an op-amp, VCO, and CMOS inverter that the method consistently reduces the length of each test by an average of 93%. Our technology can compress tests in the presence of process variation and utilize parallel processing to speed up the compression algorithm.

• 出版日期2017-6