A 3.03 mu W 10-BIT 200 KS/s SAR ADC IN 0.18 mu M CMOS

作者：Zhu, Zhangming^*; Xiao, Yu; Liang, Liang; Liu, Lianxi; Yang, Yintang

来源：Journal of Circuits, Systems, and Computers, 2013, 22(4): 1350026.

DOI：10.1142/S0218126613500266

• Successive approximation register analog to digital converter
• low power
• switching sequence
• fully dynamic comparator
• CMOS

Based on TSMC 0.18 mu m 1.8V CMOS process, a low power 10-bit 200 KS/s successive approximation register (SAR) analog-to-digital (ADC) is realized. This paper mainly considers the improvement of linearity and the optimization of power consumption. And a novel switching sequence is proposed which allows both to achieve a better compromise. Moreover, the fully dynamic comparator, which consumes no static power, and the optimization of SAR control logic, further reduce power consumption. The simulation results show that at 1.0V supply and 200 KS/s, the ADC achieves an signal-to-noise and distortion-ration (SNDR) of 59.78 dB and consumes 3.03 mu W, resulting in a figure-of-merit (FOM) of 19.0 fJ/conversion-step. The ADC core occupies an active area of only 260 x 220 mu m(2).

• 出版日期2013-4
• 单位西安电子科技大学