A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme

作者：Bai Xu^*; Okada Nobuaki; Kameyama Michitaka

来源：Journal of Multiple-Valued Logic and Soft Computing, 2013, 20(1-2): 1-18.

• Digit-serial architecture
• Fine-grain reconfigurable VLSI
• Multiple-valued VLSI
• High throughput
• Multiple-valued source-coupled logic
• MOS current-mode logic
• Low power consumption

A high-throughput recontigurable VLSI using a digit-serial architecture is proposed, where two-bit data for each operand enters a cell per clock cycle. The interconnection complexity between two adjacent cells is reduced by using a quaternary inter-cell data transfer scheme. In a cell, the quaternary data is converted into binary dual-rail voltage signals, and hi nary-controlled current steering technique is introduced utilizing a programmable three-level differential-pair circuit to implement an arbitrary two-variable binary logic function and a full-adder sum/carry. In the cell output circuit, switched current sources are used to reduce power dissipation. Moreover, the CMOS logic is used to make driving capability of a ID flip-flop high. As a result, the maximum throughput of the proposed digit-serial reconfigurable VLSI using quaternary cells is twice that of the bit-serial reconfigurable VLSI, while the power-delay product is reduced to 74%. Dramatic improvement of the recontigurable VLSI can be achieved.

• 出版日期2013